ECLair is an in-progress project by sen to design and build an ECL minicomputer. This site holds the documentation for the project, as well as a log of work being completed.
As of mid-2019 the project has a timing simulator and a functional simulator, the basic architecture and desired list of instructions is complete, and writing microcode for these instructions is almost complete. A backend for LLVM has been developed, which is now serving as the primary assembler for the CPU. A custom regression test framework using Icarus Verilog is used during development to ensure everything works as designed, and uses the aforementioned LLVM toolchain to generate test cases.
Current work is on interrupt and fault support, as well as finishing the hardware design that will support demand paging.