Microcode & Control Store

ECLair is a microcoded CPU, and the microcode is stored in the control store. The control store that the system runs from normally is in RAM, as ROMs aren’t fast enough to run the system at the goal of 25MHz. At system startup, the contents of microcode EPROMs is copied to the control store RAM before the reset line is released.

The RAM control store is writable at run-time, enabling new instructions to be added or modified on the fly.

Microcode Bits

Bit #WidthFunctionDetails
Edge Sensitive Signals
01Write Page Table EntryWrite page table entry, address in D, data to write in A
11MDR LoadLatches data or Z (determined by bit 34) into byte of MDR (determined by bit 24)
31MAR LoadMAR latch load (source specified by bit 33)
41IR LoadIR latch load from data bus
7-93Register Load from Z000 - None
001 - A
010 - B
011 - C
100 - D
101 - SP
110 - DP
111 - Value from IR[6..7] (only A-D)
101X LoadLoad register X from XY bus
111Y LoadLoad register Y from XY bus
131PTB LoadLoad PTB from Z
141RPT ExecuteExecute operation specified in RPT Mode bit on RPT counter register
151Load Status from ALULoad ALU status into STATUS register
161Clear Interrupt Flags from Z1 bit in Z clears that interrupt flag
171Memory Write
181Load Flag PELoads PE flag from Z[0]
191Load Flag MLoads M flag from Z[1]
201Load Flag IELoads IE flag from Z[2]
Level Sensitive Signals
24-329Next CS Address0 = Use IR
331MAR Sourcelow = Z, high = PC
341MDR Sourcelow = Z, high = data bus
351ALU Mode0 = Arithmetic, 1 = Logic
36-393ALU OperationTBD
40-434XY Bus Source0000 - Immediate Value (LSB from bit 24)
0001 - A
0010 - B
0011 - C
0100 - D
0101 - SP
0110 - MAR
0111 - MDR
1000 - IntVect
1001 - MAR via Shift Right path
1010 - MAR via Sign Extend path
1011 - MAR via Swap Bytes path
1100 - DP
1110 - Select register from RR[3:0]
1111 - Select register from IR[6..7] (only A-D)
441Carry InCarry input for the ALU (used to carry in a 1 to let the ALU subtract)
451Operation Width0 = 8-bit, 1 = 16-bit
46-483Branch Condition000 - Unconditional
001 - Z
010 - OC
011 - E
49-502XY Bus Immediate LSBsUsed if 40-43 = 000
511RPT Modelow = Load from MDR (all 12 bits if op_16bit, just low 8 with rest forced to zero if !op_16bit)
high = Decrement
521Register Byte Selectlow = low byte for 8bit ops, high = high byte for 8bit ops
531Memory Read
54-574Next CS Address Low Bits if RPT=00000 = No branch
0001-1111 = Use these 4 low bits instead of the lowest 4 bits of Next CS Address if RPT=0
581Write CS WordActivates the Control Store Write Sequencer, writes to CS address in SP, data in A-D.
591Increment PCIncrement PC by 1
601Load PCPC counter load from Z
611MDR Byte Selectlow = low byte for 8bit ops, high = high byte for 8bit ops
621Branch Negate0 = Normal Branch, 1 = Negate Branch Condition