Instruction Set

Currently all instructions are 8 bits wide with a variable number of immediate values after, but this will likely change at some point in the future to variable length instructions for some of the more complex ones that affect two different registers.

Category	Instruction	Format	Param 1	Param 2	Operand 1	Operand 2
Flow	call	ImmWord			MSB of immediate value to jump	LSB of immediate value to jump
Flow	jmp	ImmWord			MSB of immediate value to jump	LSB of immediate value to jump
Flow	jmpno	ImmWord			MSB of immediate value to jump	LSB of immediate value to jump
Flow	jmpnz	ImmWord			MSB of immediate value to jump	LSB of immediate value to jump
Flow	jmpne	ImmWord			MSB of immediate value to jump	LSB of immediate value to jump
Flow	jmpo	ImmWord			MSB of immediate value to jump	LSB of immediate value to jump
Flow	jmpz	ImmWord			MSB of immediate value to jump	LSB of immediate value to jump
Flow	jmpe	ImmWord			MSB of immediate value to jump	LSB of immediate value to jump
Flow	cmp16.[1][2]	RegReg	Register A-D	Register A-D
Flow	cmp8h.[1][2]	RegReg	Register A-D	Register A-D
Flow	cmp8l.[1][2]	RegReg	Register A-D	Register A-D
Flow	pop16.pc	Basic
Flow	push16.pc	Basic
Flow	reti	Basic
Load/Store	ld16.[1]	LoadStore	Register A-D		MSB of memory location to load from	LSB of memory location to load from
Load/Store	ld8.[1][2]	LoadStore	Register A-D	l/h half	MSB of memory location to load from	LSB of memory location to load from
Load/Store	ldi16.[1]	RegImmWord	Register A-D		MSB of immediate word to load	LSB of immediate word to load
Load/Store	ldi8.[1][2]	RegImmByte	Register A-D	l/h half	Immediate value to load
Load/Store	st16.[1]	LoadStore	Register A-D		MSB of memory location to store to	LSB of memory location to store to
Load/Store	st8.[1][2]	LoadStore	Register A-D	l/h half	MSB of memory location to store to	LSB of memory location to store to
Load/Store	ldi16.dp	ImmWord			MSB of immediate word to load	LSB of immediate word to load
Math	add16.[1][2]	RegReg	Register A-D	Register A-D
Math	add8h.[1][2]	RegReg	Register A-D	Register A-D
Math	add8l.[1][2]	RegReg	Register A-D	Register A-D
Math	and16.[1][2]	RegReg	Register A-D	Register A-D
Math	and8h.[1][2]	RegReg	Register A-D	Register A-D
Math	and8l.[1][2]	RegReg	Register A-D	Register A-D
Math	inv16.[1]	Reg	Register A-D
Math	inv8.[1][2]	Reg	Register A-D	l/h half
Math	or16.[1][2]	RegReg	Register A-D	Register A-D
Math	or8h.[1][2]	RegReg	Register A-D	Register A-D
Math	or8l.[1][2]	RegReg	Register A-D	Register A-D
Math	sex.[1]	Reg	Register A-D
Math	shl16.[1]	RegImmByte	Register A-D		Number of bits to shift by
Math	shl8.[1][2]	RegImmByte	Register A-D	l/h half	Number of bits to shift by
Math	shr16.[1]	RegImmByte	Register A-D		Number of bits to shift by
Math	shr8.[1][2]	RegImmByte	Register A-D	l/h half	Number of bits to shift by
Math	sub16.[1][2]	RegReg	Register A-D	Register A-D
Math	sub8h.[1][2]	RegReg	Register A-D	Register A-D
Math	sub8l.[1][2]	RegReg	Register A-D	Register A-D
Math	swab.[1]	Reg	Register A-D
Math	xor16.[1][2]	RegReg	Register A-D	Register A-D
Math	xor8h.[1][2]	RegReg	Register A-D	Register A-D
Math	xor8l.[1][2]	RegReg	Register A-D	Register A-D
Paging	ldi8.ptb	ImmByte			Immediate value to load
Paging	wrpte	Basic
Stack	ldi16.sp	ImmWord			MSB of immediate word to load	LSB of immediate word to load
Stack	push16.imm	ImmWord			MSB of immediate value to push	LSB of immediate value to push
Stack	push8.imm	ImmByte			Immediate byte to push