Decided to start tackling load/store today, which should be a lot of microcode and not much hardware work. Implemented the DP/data pointer register (had always been planned, but hadn’t needed it yet so it wasn’t there), which all load/store operations will be relative to. Implemented load and store 16-bit operations between memory and registers, and extended the toolchain somewhat to support various aspects of testing this.
Loads and stores are quite inefficient currently, as there’s no way to increment MAR without loading it into X, loading an immediate into Y, then running it through the ALU and back into MAR. Worked on converting MAR into a counter register for a bit, but it’s in the critical path so often that sync-load counters don’t really work, the level-sensitive load is really important for MAR vs. edge-sensitive like counters are. Backed out the work towards this, will have to consider what the best option is there, because currently it’s just under 10 cycles to load or store a 16-bit word, which is way too much for a load/store architecture.
Next up I’ll probably finish the 8-bit versions of load and store, then figure out how to optimize these.