Microcode & Control Store
ECLair is a microcoded CPU, and the microcode is stored in the control store. The control store that the system runs from normally is in RAM, as ROMs aren’t fast enough to run the system at the goal of 25MHz. At system startup, the contents of microcode EPROMs is copied to the control store RAM before the reset line is released.
The RAM control store is writable at run-time, enabling new instructions to be added or modified on the fly.
Microcode Bits
| Bit # | Width | Function | Details |
|---|---|---|---|
| Edge Sensitive Signals | |||
| 0 | 1 | Write Page Table Entry | Write page table entry, address in D, data to write in A |
| 1 | 1 | MDR Load | Latches data or Z (determined by bit 34) into byte of MDR (determined by bit 24) |
| 2 | 1 | AVAILABLE FOR USE | |
| 3 | 1 | MAR Load | MAR latch load (source specified by bit 33) |
| 4 | 1 | IR Load | IR latch load from data bus |
| 5 | 1 | AVAILABLE FOR USE | |
| 6 | 1 | AVAILABLE FOR USE | |
| 7-9 | 3 | Register Load from Z | 000 - None 001 - A 010 - B 011 - C 100 - D 101 - SP 110 - DP 111 - Value from IR[6..7] (only A-D) |
| 10 | 1 | X Load | Load register X from XY bus |
| 11 | 1 | Y Load | Load register Y from XY bus |
| 12 | 1 | AVAILABLE FOR USE | |
| 13 | 1 | PTB Load | Load PTB from Z |
| 14 | 1 | RPT Execute | Execute operation specified in RPT Mode bit on RPT counter register |
| 15 | 1 | Load Status from ALU | Load ALU status into STATUS register |
| 16 | 1 | Clear Interrupt Flags from Z | 1 bit in Z clears that interrupt flag |
| 17 | 1 | Memory Write | |
| 18 | 1 | Load Flag PE | Loads PE flag from Z[0] |
| 19 | 1 | Load Flag M | Loads M flag from Z[1] |
| 20 | 1 | Load Flag IE | Loads IE flag from Z[2] |
| Level Sensitive Signals | |||
| 24-32 | 9 | Next CS Address | 0 = Use IR |
| 33 | 1 | MAR Source | low = Z, high = PC |
| 34 | 1 | MDR Source | low = Z, high = data bus |
| 35 | 1 | ALU Mode | 0 = Arithmetic, 1 = Logic |
| 36-39 | 3 | ALU Operation | TBD |
| 40-43 | 4 | XY Bus Source | 0000 - Immediate Value (LSB from bit 24) 0001 - A 0010 - B 0011 - C 0100 - D 0101 - SP 0110 - MAR 0111 - MDR 1000 - IntVect 1001 - MAR via Shift Right path 1010 - MAR via Sign Extend path 1011 - MAR via Swap Bytes path 1100 - DP 1110 - Select register from RR[3:0] 1111 - Select register from IR[6..7] (only A-D) |
| 44 | 1 | Carry In | Carry input for the ALU (used to carry in a 1 to let the ALU subtract) |
| 45 | 1 | Operation Width | 0 = 8-bit, 1 = 16-bit |
| 46-48 | 3 | Branch Condition | 000 - Unconditional 001 - Z 010 - OC 011 - E |
| 49-50 | 2 | XY Bus Immediate LSBs | Used if 40-43 = 000 |
| 51 | 1 | RPT Mode | low = Load from MDR (all 12 bits if op_16bit, just low 8 with rest forced to zero if !op_16bit) high = Decrement |
| 52 | 1 | Register Byte Select | low = low byte for 8bit ops, high = high byte for 8bit ops |
| 53 | 1 | Memory Read | |
| 54-57 | 4 | Next CS Address Low Bits if RPT=0 | 0000 = No branch 0001-1111 = Use these 4 low bits instead of the lowest 4 bits of Next CS Address if RPT=0 |
| 58 | 1 | Write CS Word | Activates the Control Store Write Sequencer, writes to CS address in SP, data in A-D. |
| 59 | 1 | Increment PC | Increment PC by 1 |
| 60 | 1 | Load PC | PC counter load from Z |
| 61 | 1 | MDR Byte Select | low = low byte for 8bit ops, high = high byte for 8bit ops |
| 62 | 1 | Branch Negate | 0 = Normal Branch, 1 = Negate Branch Condition |
| 63 | 1 | DMA Acknowledge | |