As I started looking at adding ECLair’s instructions to the LLVM port, I realized that a lot of them aren’t organized in a reasonable way. For example, add16 with the source/dest register A has an entirely different pattern of bits than with a source/dest register of B, even the bits that aren’t the register selector. This would have made it annoying to get the toolchain to understand it.

I shuffled add16 around tonight so that the bit pattern is the same (0b00010000) for all forms of it, and just the register selector bits change for add16.a? vs add16.b? etc.

I’ll have to do this for a lot of instructions, but so far I’ve just taken care of that one, as add16 was required to be implemented to even get the toolchain to compile, which is my first goal.