Disassembler working!
Looking into the toolchain more, the next step after the assembler seemed to be a disassembler. LLVM handles a lot of the details of this using the same data tables created for the assembler, so it seemed like it wouldn’t […]
Looking into the toolchain more, the next step after the assembler seemed to be a disassembler. LLVM handles a lot of the details of this using the same data tables created for the assembler, so it seemed like it wouldn’t […]
I took a break for a few days from working on the design itself, to work on a tool to generate a graph of the simulator signal flow. The signal flow in parts of the CPU is getting complicated enough […]
Finished off the rewrite of the microcode assembler yesterday, the new one has now taken over as the reference implementation and is the primary microcode assembler used by the simulator. I still want to implement some optimization features later on, […]
The new LLVM-based assembler is fully working, and 100% of the regression tests have been moved over to it as of this afternoon. It took close to 9 months to get done, but it’s all working now and gives us […]
I’ve spent the last few evenings tweaking the LLVM backend’s MC code to fix a lot of minor issues, and it’s to the point where it can generate normal output from ECLair assembly input now! It understands that different instructions […]
Worked on the LLVM backend a bunch more this evening, and it successfully assembled something for the first time! Halt is just 0xfe but the backend only understands 16-bit instructions at the moment, so it assembled as noop, halt, but […]
I haven’t made any posts here in ages, but that doesn’t mean that work hasn’t been happening behind the scenes! I looked at what my options were last fall when it came to assemblers, and it looked like I had […]
Started working on the implementation of jmpe/jmpne, got frustrated that the temporary assembler still doesn’t support two-byte instructions. Fixed this, it now looks at the opcode and figures out which instruction will require a second register-selector byte and handles this […]
As I started looking at adding ECLair’s instructions to the LLVM port, I realized that a lot of them aren’t organized in a reasonable way. For example, add16 with the source/dest register A has an entirely different pattern of bits […]
I’ve spent a bunch of my spare time over the past few months figuring out a toolchain for ECLair. I’m using LLVM so far, and have been working on learning how to port it to a new target platform and […]