Implemented high-byte loads for the 8-bit registers, tests for these all now exist and pass.

Started thinking about implementing shifts, looked at barrel shifters but they’re far too much logic for now (~64 muxes, which would be ~128 chips), and I can always add one as an extension later.

Next step will be to figure out the slight mess of the XY bus, currently it uses a big mux but it looks like the best way is going to be for each signal that can drive XY to go through a MC10E143 latch, and use the async reset to zero it out when it’s not driving the bus, then wired-OR the outputs all together. Wired-OR makes the V_IL noise margin worse, but per the formula in the DEC WRL Research Report 90/1 (0.03*ln(n) where n is the number of gates) this shouldn’t be a problem at the number of gates I’d be looking at for the XY bus.