Timing simulator now has accurate timing

Implemented realistic propagation delays for most parts (main EPROM and ALU not done yet), and fixed a bunch of bugs related to previous lack of delays.

Have a hacked-in delay for cs_jump right now, next step will be to split the microcode into 24 “edge-sensitive signal bits” and 40 “level-sensitive signal bits”, and clock the former slightly after the latter. This will avoid needing two separate microcode instructions to set up level-sensitive signals then trigger the edge-sensitive ones. Doing this will mean a complete reorganization order-wise of the microcode though.