ECLair

Custom ECL CPU

  • About ECLair
  • System Overview
  • Microcode & Control Store
  • Instruction Set
  • Registers
  • Paging Subsystem
  • Expansion/Extension Slots
  • Work Log
  • About ECLair
  • System Overview
  • Microcode & Control Store
  • Instruction Set
  • Registers
  • Paging Subsystem
  • Expansion/Extension Slots
  • Work Log

Month: December 2012

Paging works!

December 26, 2012April 29, 2018

Implemented ldi8.flags so that paging can be turned on. Fixed a couple bugs in the system, and now paging works! Also while working on this, I renamed PID to PTB (page table block) as one PID could potentially use more […]

sen Design Log

Started work on paging

December 25, 2012April 29, 2018

Worked out details on the paging system, added it to the schematic, and implemented it. The system can now ldi8.pid to load the current PID into the PID register, then wrpte to load the first entry in the page table. […]

sen Design Log

Finished reworking microcode sequencing

December 23, 2012April 29, 2018

Worked out the right way to fix the sequencing issue/dependency between microcode signals, now the level-sensitive signals (bits 0-23) latch first, then the edge-sensitive signals (bits 24-63) latch, then the edge-sensitive signals are reset back to 0 so they don’t […]

sen Design Log

More work on microcode sequencing

December 22, 2012April 29, 2018

Hacked on the sequencing issue more today, made no real progress.

sen Design Log

Split microcode into edge and level-sensitive areas

December 21, 2012April 29, 2018

Reordered microcode bits into 24 bits for edge-sensitive signals and 40 for level-sensitive signals. Redesigned the microcode sequencer to use a latch and an always-populated next_addr bit field rather than a counter, which solves many problems around jumping and runt […]

sen Design Log

Timing simulator now has accurate timing

December 20, 2012April 29, 2018

Implemented realistic propagation delays for most parts (main EPROM and ALU not done yet), and fixed a bunch of bugs related to previous lack of delays. Have a hacked-in delay for cs_jump right now, next step will be to split […]

sen Design Log

Finished 8/16bit selection

December 19, 2012April 29, 2018

Finished implementing 8/16-bit width selection and got the bugs worked out. Now we have 8-bit and 16-bit immediate loads, and 8-bit loads don’t trash the other 8 bits of the destination register. Still need to get 8-bit high-byte load implemented. […]

sen Design Log

Started working on 8/16 bit flag

December 18, 2012April 29, 2018

Half-implemented 8/16-bit width selection using a microcode bit. Doesn’t work at all yet.

sen Design Log

Added ability to select a register from IR bits

December 17, 2012April 29, 2018

Implemented a data path from IR[7:6] to the register latch signals, so that all register-related operations can be simplified in microcode. Moved the ldi* instructions to use this new path, everything is tested and working. Next step is probably to […]

sen Design Log

Implemented the MDR-XY data path and first bits of instruction microcode

December 16, 2012April 29, 2018

MDR-XY data path implemented, Load Immediate 8-bit values to A and B instructions written, add 16-bit A=A+B written, all working.

sen Design Log

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Work Log

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