Worked out details on the paging system, added it to the schematic, and implemented it. The system can now ldi8.pid to load the current PID into the PID register, then wrpte to load the first entry in the page table. […]

Worked out the right way to fix the sequencing issue/dependency between microcode signals, now the level-sensitive signals (bits 0-23) latch first, then the edge-sensitive signals (bits 24-63) latch, then the edge-sensitive signals are reset back to 0 so they don’t […]

Hacked on the sequencing issue more today, made no real progress.

Reordered microcode bits into 24 bits for edge-sensitive signals and 40 for level-sensitive signals. Redesigned the microcode sequencer to use a latch and an always-populated next_addr bit field rather than a counter, which solves many problems around jumping and runt […]

Implemented realistic propagation delays for most parts (main EPROM and ALU not done yet), and fixed a bunch of bugs related to previous lack of delays. Have a hacked-in delay for cs_jump right now, next step will be to split […]

Finished implementing 8/16-bit width selection and got the bugs worked out. Now we have 8-bit and 16-bit immediate loads, and 8-bit loads don’t trash the other 8 bits of the destination register. Still need to get 8-bit high-byte load implemented. […]

Half-implemented 8/16-bit width selection using a microcode bit. Doesn’t work at all yet.

Implemented a data path from IR[7:6] to the register latch signals, so that all register-related operations can be simplified in microcode. Moved the ldi* instructions to use this new path, everything is tested and working. Next step is probably to […]

MDR-XY data path implemented, Load Immediate 8-bit values to A and B instructions written, add 16-bit A=A+B written, all working.

Found a bug in the datasheet of the MC10H181, fixed it and now the ALU checks out completely. Started integrating it into the CPU. Next step is to finish the MDR-XY data path so that Load Immediate instruction can be […]