ECLair

Custom ECL CPU

  • About ECLair
  • System Overview
  • Microcode & Control Store
  • Instruction Set
  • Registers
  • Paging Subsystem
  • Expansion/Extension Slots
  • Work Log
  • About ECLair
  • System Overview
  • Microcode & Control Store
  • Instruction Set
  • Registers
  • Paging Subsystem
  • Expansion/Extension Slots
  • Work Log

Category: Design Log

Shift 16-bit left works for all registers

April 24, 2018April 29, 2018

Shift 16-bit register left now works for registers B-D as well, and has working unit tests. The RPT counter register has also been expanded to 12 bits, so in hardware we’ll build it with two 6-bit chips. This isn’t needed […]

sen Design Log

Shift 16-bit left done

April 22, 2018April 29, 2018

Shift 16-bit register left now fully works with any number of bits! Next step is to implement the tests for registers B-D, then implement byte-wide left shifts. Should also decide if the RPT counter register will be 6 bits or […]

sen Design Log

Shift left starting to work

April 21, 2018April 29, 2018

Shift left now works when shifting by 1 bit! Next step will be to implement very simple conditional jumps in microcode based on RPT, so that multiple shifts can be done in one instruction.

sen Design Log

Started working on first shift microcode

April 20, 2018April 29, 2018

Started working on shl16.a. The first bits of microcode work are implemented for a single-bit left shift, including a simple test case, but the CPU runs away during the test. Next step will be troubleshooting this more to figure out […]

sen Design Log

RPT implemented

April 6, 2018April 29, 2018

Implemented the new RPT counter register in the timing simulator, haven’t tested it yet but it passes all existing regression tests at least.

sen Design Log

Started implementing RPT counter register

April 5, 2018April 29, 2018

Added work done on 2018-04-03 to the functional simulator. Also added RPT register for things the microcode has to do more than once (like the upcoming shift operations). Haven’t implemented anything yet, but started thinking about it and will probably […]

sen Design Log

XY Nibble microcode bit is gone

April 3, 2018April 29, 2018

Eliminated the separate XY Nibble microcode bit and associated logic, and integrated intvect directly as xy_src=8. All tests still passing. The functional simulator still needs to be updated for this change.

sen Design Log

Big XY Mux is finally gone!

April 2, 2018April 29, 2018

The big XY mux is finally gone! I’ve been bumping up against limits in this part of the design since 2014-06-03, but it’s all sorted out now. I moved the Memory Read bit in microcode up to make room to […]

sen Design Log

Started thinking about implementing shifts

April 1, 2018April 29, 2018

Implemented high-byte loads for the 8-bit registers, tests for these all now exist and pass. Started thinking about implementing shifts, looked at barrel shifters but they’re far too much logic for now (~64 muxes, which would be ~128 chips), and […]

sen Design Log

Though about changing to 9/18 bit bytes/words

March 31, 2018April 29, 2018

Thought a lot about whether 64k per page table block is really enough space, extensively considered going to 9bit bytes and 18bit alu/registers. Eventually decided against it after a lot of consideration, as I think it would make interop with […]

sen Design Log

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Work Log

  • November 2024
  • August 2024
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  • May 2021
  • November 2020
  • July 2019
  • April 2019
  • November 2018
  • October 2018
  • May 2018
  • April 2018
  • March 2018
  • July 2017
  • December 2016
  • July 2015
  • June 2015
  • June 2014
  • May 2014
  • December 2013
  • May 2013
  • February 2013
  • January 2013
  • December 2012
  • November 2012
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