Was pretty much out of microcode space, so extended the address width from 8 bits to 9. I’d known for awhile that this would likely be needed, as I exceeded 80% of the microcode space used up before even hitting 50% of the instructions implemented. Worked out the few issues this caused, and everything is working at 9 bits now. Entry points for instructions have to be in the first 256 instructions as IR is still only 8 bits wide, but instructions can then jump into the ‘high area’ and continue from there, as next_addr is 9 bits. Shuffled some of the microcode around to free up space in the lower half, so there’s plenty of room for instruction entry points now.

Implemented the RR register (register register), which is similar to IR but for the second byte of multi-byte instructions. These will be used for instructions that use two different registers, the IR register field is used for the first/destination register, and the low nibble of the second byte (which gets stored in RR) is used for the source of the second register. I’ve re-worked the add16.ab instruction to use this new way of doing things, rather than hard-coding both registers like add16.ab used to.

The assembler doesn’t support multi-byte instructions yet, so right now the assembly code for add16.ab has to be followed with a data byte specifying the second source register:

add16.ab
data 0x01

Next up I need to work on getting the assembler to support multi-byte instructions, as this needs to be done before implementing even more of them. I may look at doing a proper assembler port now, rather than extending seasm further (as it was always intended to be a stopgap), but we’ll see.