I took a break for a few days from working on the design itself, to work on a tool to generate a graph of the simulator signal flow. The signal flow in parts of the CPU is getting complicated enough that I’m losing track of how it works, and I wanted something to help visualize that.

It’s mostly done in basic form now, and uses graphviz to plot all module instances as nodes, with all wires as edges between them. The overall graph is a bit “busy” to be very useful in its current form, since there are so many signals all over the place it’s hard to trace one from end to end. The next step I want to do with this tool is to be able to add filters, so you can tell it to show one signal from end to end, or a specific set of nodes and the signals between them.

One thing that stands out to me looking at the overall diagram is how many small bits of glue logic there are (represented by filled black circles), many of which will have to be broken out into specific chips as things move into real hardware. One advantage of ECL is that you can just wire signals together to OR them and you often don’t need inverters since many of the signals are differential pairs, so some of these dots won’t actually need hardware.

I’m going to call this tool good enough for the time being, and move on to implementing syscalls or exceptions next.