Writable control store implementation done

Had a lot of TODO items to finish up the writable control store after last time, so took care of all of them today.

After thinking about how to implement switching the data input lines for the CS RAM from the EPROM outputs (at power-on, so the RAMs can be loaded) to the A-D registers (so we can write at runtime), I realized that since this is ECL, I can just have an entry in the ROM that is all zeroes and connect the two directly together as ECL allows for wired-OR. I’ve implemented the blank area at control store address 255 (which was blank anyways due to how the boot-time copier works), and everything seems to work well.

Thought for awhile about how to best build a counter that brought each bit high one after another rather than doing actual binary counting counting, then eventually realized I was trying to reinvent a shift register. I re-implemented the control store write sequencer using a shift register rather than a counter, which simplifies the logic around it a bunch and also makes control store writes significantly faster now.

I also took care of cleaning up the code a lot, the control store write sequencer is now all in one place in the code and properly commented. The unit test framework has also been updated to be able to test a specific control word value, and the unit test for wrcse has been updated to use this functionality, so it’s actually a full working test case now.

Next up I’ll probably go back to implementing instructions for a bit, next up is shift right, then store (opposite of the ld* instructions). At some point whenever I’m tired of implementing instructions, I need to go back and finish implementing interrupts as well.