After the last bit of thinking about the writable control store, I decided to leave it for a few days and think about it more before implementing anything, because none of the designs I’d come up with seemed practical (either requiring 16+ extra chips or dual port RAM, which doesn’t exist in ECL so would require CMOS RAM and logic family bridging to implement).
After thinking a bunch today while in transit, I came up with just implementing a very simple sequencer (using a counter and some glue logic) that will take over control of the microcode and some clocks, perform the write sequence, then hand control back to the main CPU. This should be a lot simpler than having to switch a lot of connections around including the main clocks at runtime, just to allow the normal microcode to perform the write sequence.
The basic sequence (once initiated via a microcode bit) will be:
- Hold the microcode clock steady to keep the latches in their current state.
- Switch cs_addr to the alternate source (SP for now probably, since we’re using A-D for microcode data already).
- Perform a write on the control store.
- Switch cs_addr back to the normal source.
- Release the microcode clock to resume normal operation.
Got the basic functionality in place this evening, the sequencer is in place and runs through most of the steps listed above. The data lines are not hooked up from A-D yet so it’s just writing junk data, but the address and clock rerouting seems to all work.
- Implement switching the data input lines from the CS EPROMs to A-D once the control store completes power-on initialization.
- Clean up the code, currently cswrite_step is directly referenced all over the place which is hard to read, should set up some ‘wire’s with names that make sense and assign them all in one place instead.
- Implement a proper test, currently the test does the things but doesn’t check that the control store actually got modified.
- Consider optimizing the control store write sequencer, currently it’s an overly simplistic one-hot state encoding using one bit from a counter for each state, but this means that step 2 takes twice as long as step 1, step 3 takes twice as long as step 2, etc. Speed isn’t a priority for control store writes, but it would be nice if it was a bit cleaner than it is now, if there’s a way to do that without adding too much extra logic.