Thoughts on the writable control store

Implemented ability to choose a register to drive the XY bus using IR[7:6], which is the retrieval equivalent of what we’ve been able to do storage-wise for ages now. This will simplify a bunch of things and only added one extra decoder chip. The high byte shift left instructions are now implemented and working using this as well.

Next task will probably work on the wrcse instruction, as a break from shifts before returning to implement shift right. I initially thought this would be simple, but as soon as I started thinking about how to implement it I realized it actually won’t be. To write to the control store RAM (unless it’s dual-port RAM, which I don’t want to get into if it can be avoided), the control store address bus would need to be changed to the address to write to, at which point control of the CPU is lost because execution will jump to a (presumably) blank area of the control store. My current thought on this is to somehow switch execution to run directly from EPROM for a few steps (and switch the clock to the slower initialization clock to allow this to work, since EPROM is slow), decouple the cs_addr bus from the control store RAM, do the write, then undo the changes. Will be a pain to implement, but it’s a cool feature to have, and a critical part of the Extension Bus idea I have.