Interrupts are working!
Spent a bunch of today working on microcode and a unit test for interrupts, and got it all working! There are now 8 working interrupt lines that support separate ISRs for each and have a priority system, and there’s a […]
Author: sen
Instruction implementation mostly complete!
Finished off the rewrite of the microcode assembler yesterday, the new one has now taken over as the reference implementation and is the primary microcode assembler used by the simulator. I still want to implement some optimization features later on, […]
Microcode assembler work
I’ve spent a bit of time over the past couple of months re-implementing the microcode assembler from scratch. The original microcode assembler was thrown together to save me from typing 64 ones and zeroes for every word of microcode (which […]
Microcode getting close to complete
I implemented the microcode for the 16 bit, 8 bit low, and 8 bit high variants of AND, OR, and XOR this evening, which went smoothly (if a bit tediously). At this point 47 instructions are implemented in microcode, and […]
Assembler fully working
The new LLVM-based assembler is fully working, and 100% of the regression tests have been moved over to it as of this afternoon. It took close to 9 months to get done, but it’s all working now and gives us […]
Assembler progress
I’ve spent the last few evenings tweaking the LLVM backend’s MC code to fix a lot of minor issues, and it’s to the point where it can generate normal output from ECLair assembly input now! It understands that different instructions […]
First successful assembly
Worked on the LLVM backend a bunch more this evening, and it successfully assembled something for the first time! Halt is just 0xfe but the backend only understands 16-bit instructions at the moment, so it assembled as noop, halt, but […]
Lots more toolchain work
I haven’t made any posts here in ages, but that doesn’t mean that work hasn’t been happening behind the scenes! I looked at what my options were last fall when it came to assemblers, and it looked like I had […]
More random reorganizing and a lot more toolchain work
Started working on the implementation of jmpe/jmpne, got frustrated that the temporary assembler still doesn’t support two-byte instructions. Fixed this, it now looks at the opcode and figures out which instruction will require a second register-selector byte and handles this […]
More branch/compare work
While thinking about the toolchain I realized I hadn’t ever finished implementing branch instructions. Today I added a microcode bit to negate branching (for the ‘if not’ jump instructions), and implemented the jmpnz and jmpno instructions. Also updated the test […]