Had a lot of TODO items to finish up the writable control store after last time, so took care of all of them today. After thinking about how to implement switching the data input lines for the CS RAM from the […]
After the last bit of thinking about the writable control store, I decided to leave it for a few days and think about it more before implementing anything, because none of the designs I’d come up with seemed practical (either […]
Spent a bunch of time this weekend putting the website for ECLair together. Up until now all of the documentation was a mix of files in the git repository, one wiki page on my projects wiki, and various Google Sheets, […]
Implemented ability to choose a register to drive the XY bus using IR[7:6], which is the retrieval equivalent of what we’ve been able to do storage-wise for ages now. This will simplify a bunch of things and only added one […]
Instruction to shift low byte of registers left now works and has unit tests. Started working on the instruction to shift the high byte of registers left. This is still a work in progress, currently it shifts junk from the […]
Shift 16-bit register left now works for registers B-D as well, and has working unit tests. The RPT counter register has also been expanded to 12 bits, so in hardware we’ll build it with two 6-bit chips. This isn’t needed […]
Shift 16-bit register left now fully works with any number of bits! Next step is to implement the tests for registers B-D, then implement byte-wide left shifts. Should also decide if the RPT counter register will be 6 bits or […]
Shift left now works when shifting by 1 bit! Next step will be to implement very simple conditional jumps in microcode based on RPT, so that multiple shifts can be done in one instruction.
Started working on shl16.a. The first bits of microcode work are implemented for a single-bit left shift, including a simple test case, but the CPU runs away during the test. Next step will be troubleshooting this more to figure out […]
Implemented the new RPT counter register in the timing simulator, haven’t tested it yet but it passes all existing regression tests at least.