ECLair

Custom ECL CPU

  • About ECLair
  • System Overview
  • Microcode & Control Store
  • Instruction Set
  • Registers
  • Paging Subsystem
  • Expansion/Extension Slots
  • Work Log
  • About ECLair
  • System Overview
  • Microcode & Control Store
  • Instruction Set
  • Registers
  • Paging Subsystem
  • Expansion/Extension Slots
  • Work Log

Author: sen

Shuffled instructions a bit

October 31, 2018November 1, 2018

As I started looking at adding ECLair’s instructions to the LLVM port, I realized that a lot of them aren’t organized in a reasonable way. For example, add16 with the source/dest register A has an entirely different pattern of bits […]

sen Design Log, Toolchain

Toolchain Work

October 31, 2018November 1, 2018

I’ve spent a bunch of my spare time over the past few months figuring out a toolchain for ECLair. I’m using LLVM so far, and have been working on learning how to port it to a new target platform and […]

sen Design Log, Toolchain

Microcode address width extended, multi-byte instructions working

May 13, 2018

Was pretty much out of microcode space, so extended the address width from 8 bits to 9. I’d known for awhile that this would likely be needed, as I exceeded 80% of the microcode space used up before even hitting […]

sen Design Log, Toolchain

Load/store is done (for now)

May 12, 2018May 13, 2018

Finished all the 8-bit load and store operations, everything has proper unit tests and is working. While doing this it was starting to get hard to manage the single microcode definition file as it’s almost 650 lines long, and it’s […]

sen Design Log

Lots of work on load/store today

May 11, 2018May 11, 2018

Decided to start tackling load/store today, which should be a lot of microcode and not much hardware work. Implemented the DP/data pointer register (had always been planned, but hadn’t needed it yet so it wasn’t there), which all load/store operations […]

sen Design Log

Instruction implementation spree!

May 9, 2018

Sat down and wrote out a bunch of microcode tonight, and added a couple more required transformation data paths from MAR to XY (byte swap and sign extend). Binary inversion (NOT) is implemented now in both 8/16 bit forms, as […]

sen Design Log

Cleaned up a few TODO items

May 7, 2018

Spent a bit of time implementing the “clear all internal registers” function and added it into some unit tests, which should result in more accurate testing/catching some edge cases we wouldn’t have caught before. Also simplified the return path for […]

sen Design Log

Shift right instructions

May 6, 2018July 13, 2019

Implemented all the shift right instructions this evening, using a latch between MAR and the XY bus that just physically connects the bits shifted over by one. The code is pretty similar to the shift left code, except instead of […]

sen Design Log

Writable control store implementation done

May 6, 2018May 6, 2018

Had a lot of TODO items to finish up the writable control store after last time, so took care of all of them today. After thinking about how to implement switching the data input lines for the CS RAM from the […]

sen Design Log, Writable Control Store

First writable control store functionality implemented

May 5, 2018 1 Comment

After the last bit of thinking about the writable control store, I decided to leave it for a few days and think about it more before implementing anything, because none of the designs I’d come up with seemed practical (either […]

sen Design Log, Writable Control Store

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Work Log

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  • November 2018
  • October 2018
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  • December 2016
  • July 2015
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  • June 2014
  • May 2014
  • December 2013
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  • February 2013
  • January 2013
  • December 2012
  • November 2012
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